Faculty

Institution

Unit

Venue

Shantanu Dutt

Professor

University of Illinois Chicago

Affiliations

College of Engineering

Electrical and Computer Engineering

Shantanu Dutt is currently serving as a College Of Engineering Professor at University of Illinois Chicago.

Honors

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Experiences

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Education

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Shantanu Dutt

University of Illinois Chicago

Professor

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systems engineering electrical engineering computer engineering computer science parallel computing power electronics fault tolerance machine learning computer architecture computer-aided design distributed systems formal methods design automation reliability engineering design optimization field programmable gate array vlsi design circuit design vlsi circuit reconfigurable architectures software testing networked system design computational optimization engineering optimization distributed computing fpga design multiprocessor systems control systems mathematical optimization scientific computing electronic design distributed processing electronic engineering built-in self-test parallel processing load balancing (computing) on-line testing fault-tolerant multiprocessors provable diagnosabilities instrumentation control optimization vehicular technology defect tolerance parallel learning electronic design automation asic design asic implementation sensor placement router design router architecture system testing timing-driven incremental placement high diagnostic coverage vlsi circuit partitioning electronics automatic control graph processing computer design autonomic computing defect formation scalable computing concurrency theory resource constraints constraint programming constraint solving fault-tolerant systems k-fault-tolerant tree architectures kernighan-lin-type graph-partitioning algorithms fault tolerance methods increased yield iterative improvement techniques hypercube multiprocessor duplicate pruning local hashing strategies intermediate relaxations large vlsi circuits vlsi architecture vlsi cad

Notable Scholarly Works

Notable Federal Grants

Collaborators

A Max Weighted-Matching Based Non-Greedy Post-Hls Power Gating Technique With Comprehensive Power Modeling. (2025)

power engineeringmax weighted-matchingpower optimization (eda)energy efficiencypower-aware designcomputer engineeringcomprehensive power modelingenergy systemsintegrated circuitspower deliverypower icelectrical engineeringpower electronicsenergy managementengineeringvlsi circuit

Contributors. Elsevier eBooks (2022)

Ron AltermanJeffrey E. ArleKerry BradleySergio CanaveroSteven M. FalowskiChad W. FarleyYakov GologorskyJianwen Wendy GuH. Louis JournéeJohn KastOlga KhazenJoachim K. KraussVignessh KumarMark LentRobert M. LevyAndres M. LozanoCharles MackelGeorge T. MandyburBryan L. McLaughlinDaniel R. MerrillAlon Y. MogilnerGabi MolnarGuillermo A. MonsalveRichard B. NorthYunseo Linda ParkJohn ParkerShrey PatelJulie G. PilitsisFrancisco A. PonceJason E. PopeAdolfo Ramirez-ZamoraLouis J. RasoJoshua M. RosenowJay L. ShilsPeter SingleKonstantin V. SlavinMichael D. StaudtMark M. SteckerHuy Q. Truong

Limiting Interconnect Heating in Power-Driven Physical Synthesis. (2022)

Xiuyan ZhangShantanu Dutt

power-driven physical synthesispower electronicselectrical engineeringinterconnect heating

Session Details: Compute-In-Memory and Design of Structured Compute Arrays. (2022)

Shantanu Dutt

in-memory computingcomputer sciencestructured compute arrays

On the Correlation Between Resource Minimization and Interconnect Complexities in High-Level Synthesis. (2021)

Shantanu DuttXiuyan ZhangOuwen Shi

systems engineeringinterconnect complexitiesresource minimizationhigh-level synthesis

A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding. Journal of Low Power Electronics (2019)

Xiuyan ZhangOuwen ShiJian XuShantanu Dutt

systems engineeringcomputer engineeringlow-power electronicsformal methodsmodule selectionelectrical engineeringpower electronics

A Fast and Effective Lookahead and Fractional Search Based Scheduling Algorithm for High-Level Synthesis. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 (2018)

Shantanu DuttOuwen Shi

systems engineeringhigh-level synthesisfractional search

Power-Delay Product Based Resource Library Construction for Effective Power Optimization in Hls. (2017)

Shantanu DuttOuwen Shi

power-delay productpower electronicsresource library constructionelectrical engineering

Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis. Journal of Low Power Electronics (2016)

Ouwen ShiShantanu Dutt

high-level synthesisunit-time leakage powerlow-power electronicslatency spacespower electronicselectrical engineeringleakage energy minimizationoptoelectronicsengineering

Communication Scheduling and Buslet Synthesis for Low-Interconnect Hls Designs. International Conference on Computer Aided Design (2015)

Enzo TartaglioneShantanu Dutt

systems engineeringcomputer-aided designcommunication schedulingbuslet synthesismodeling and simulationelectrical engineeringpower electronicscomputer sciencelow-interconnect hls designs

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Shantanu Dutt

Professor

University of Illinois Chicago

Affiliations

College of Engineering

Electrical and Computer Engineering

Shantanu Dutt is currently serving as a College Of Engineering Professor at University of Illinois Chicago.

Honors

Create free account to unlock more features

Experiences

Create free account to unlock more features

Education

Create free account to unlock more features

Shantanu Dutt

University of Illinois Chicago

Professor

You can click a keyword to filter the displayed items

Notable Scholarly Works

Notable Federal Grants

Collaborators

A Max Weighted-Matching Based Non-Greedy Post-Hls Power Gating Technique With Comprehensive Power Modeling. (2025)

Contributors. Elsevier eBooks (2022)

Limiting Interconnect Heating in Power-Driven Physical Synthesis. (2022)

Xiuyan ZhangShantanu Dutt

power-driven physical synthesispower electronicselectrical engineeringinterconnect heating

Session Details: Compute-In-Memory and Design of Structured Compute Arrays. (2022)

Shantanu Dutt

in-memory computingcomputer sciencestructured compute arrays

On the Correlation Between Resource Minimization and Interconnect Complexities in High-Level Synthesis. (2021)

Shantanu DuttXiuyan ZhangOuwen Shi

systems engineeringinterconnect complexitiesresource minimizationhigh-level synthesis

A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding. Journal of Low Power Electronics (2019)

Xiuyan ZhangOuwen ShiJian XuShantanu Dutt

systems engineeringcomputer engineeringlow-power electronicsformal methodsmodule selectionelectrical engineeringpower electronics

A Fast and Effective Lookahead and Fractional Search Based Scheduling Algorithm for High-Level Synthesis. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 (2018)

Shantanu DuttOuwen Shi

systems engineeringhigh-level synthesisfractional search

Power-Delay Product Based Resource Library Construction for Effective Power Optimization in Hls. (2017)

Shantanu DuttOuwen Shi

power-delay productpower electronicsresource library constructionelectrical engineering

Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis. Journal of Low Power Electronics (2016)

Ouwen ShiShantanu Dutt

high-level synthesisunit-time leakage powerlow-power electronicslatency spacespower electronicselectrical engineeringleakage energy minimizationoptoelectronicsengineering

Communication Scheduling and Buslet Synthesis for Low-Interconnect Hls Designs. International Conference on Computer Aided Design (2015)

Enzo TartaglioneShantanu Dutt

systems engineeringcomputer-aided designcommunication schedulingbuslet synthesismodeling and simulationelectrical engineeringpower electronicscomputer sciencelow-interconnect hls designs

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5
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10 / page

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Similar Faculty Members

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Institution

University of Texas at Dallas

design methodologies

electronic design automation

Alex K. Jones

Institution

Syracuse University

computer engineering

hardware architecture

Carl Sechen

Institution

University of Texas at Dallas

computer engineering

electrical engineering

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electronic design automation

Bill Lin

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gigascale integration

computer engineering

Margaret Marek-Sadowska

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University of California, Santa Barbara

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James C. Hoe

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design automation

high-level hardware design

Janardhan Rao Jana Doppa

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Oregon State University

industrial artificial intelligence

machine learning

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systems engineering

Alex Orailoglu

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electronic design automation

field programmable gate array