Faculty

Institution

Unit

Venue

Jose Renau

Department Chair Professor Professor

University of California, Santa Cruz

Affiliations

Baskin School of Engineering

Computer Science and Engineering

Jose Renau is currently serving as a Baskin School Of Engineering Department Chair Professor Professor at University of California, Santa Cruz.

Honors

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Experiences

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Education

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Jose Renau

University of California, Santa Cruz

Department Chair Professor Professor

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computer science computer engineering electrical engineering microarchitecture parallel computing computer architecture high performance computer architecture engineering performance evaluation energy efficiency processor architectures parallel programming high-performance architectures energy management thermal engineering power electronics power-aware computing embedded systems program analysis scalability vlsi circuit design automation many-core architectures energy consumption compiler technology programming languages software analysis parallelizing compiler manycore processor thermal analysis multithreading (computer architecture) power-efficient computing electronic packaging scientific computing vlsi technology memory management instruction-level parallelism program optimization performance prediction temperature measurement thermal processing power management circuit design gpu computing memory architectures tls compiler tls compilers tls cmp positional adaptation code sections value prediction thread-level speculation dynamic energy efficiency real processors distributed systems system software energy strategies sustainable energy technologies parallel software energy-efficient technologies thermal management task parallelism performance measures performance characterization performance measurement performance scalability scalable computing hardware acceleration advanced computing tls compilation time-based sampling fast multicore simulator cherry checkpoint cherry implementation early resource key tls basics computer-aided design next generation computing technology hardware modeling electronic design automation modeling and simulation

Video Presentations

Notable Scholarly Works

Notable Federal Grants

Collaborators

Developing the Itl Framework and Committing to Inquiry as a Method for Reducing Equity Gaps in High-Impact, Computer Science and Engineering Courses. (2024)

Sagnik NathJennifer QuynnJose Renau

engineering educationequity gapscomputer scienceitl frameworkhigher educationengineering courses

A Multi-Threaded Fast Hardware Compiler for Hdls. International Conference on Compiler Construction (2023)

Sheng-Hong WangHunter James CoffmanKenneth MayerSakshi GargJose Renau

parallel computingcomputer engineeringcomputer sciencecompiler technology

Enabling Reduced Simpoint Size Through Livecache and Detail Warmup. BenchCouncil Transactions on Benchmarks Standards and Evaluations (2022)

Jose RenauFangping LiuHongzhang ShanSang Wook Stephen Do

performance benchmarkingbenchmarking toolsystems engineeringsimpoint sizebenchmark studiesmachine learningdetail warmup

Effective Processor Verification With Logic Fuzzer Enhanced Co-Simulation. IEEE/ACM International Symposium on Microarchitecture (2021)

Nursultan KabylkasTommy ThornShreesha SrinathPolychronis XekalakisJose Renau

co-simulationdefect tolerancehardware securitycomputer scienceeffective processor verificationlogic fuzzer

LIVEHD: A Productive Live Hardware Development Flow. IEEE Micro (2020)

Sheng-Hong WangRafael Trapani PossignoloHaven Blake SkinnerJose Renau

device developmentsystems engineeringengineeringembedded systemselectrical engineering

LIVESIM: A Fast Hot Reload Simulator for Hdls. (2020)

Haven SkinnerRafael Trapani PossignoloSheng-Hong WangJose Renau

Load Driven Branch Predictor (Ldbp). arXiv (Cornell University) (2020)

Akash SridharNursultan KabylkasJose Renau

decision tree learningbranch predictorapplied mathematicsmachine learning

Emi Architectural Model and Core Hopping. (2019)

Daphne I. GormanRafael Trapani PossignoloJose Renau

emi architectural modelarchitecturecore hoppingmodeling and simulationelectrical engineering

Smatch. (2019)

Rafael Trapani PossignoloJose Renau

GPU Ntc Process Variation Compensation With Voltage Stacking. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018)

Rafael Trapani PossignoloElnaz EbrahimiEhsan Khish ArdestaniAlamelu SankaranarayananJose Luis BrizJose Renau

systems engineeringengineeringvlsi technologyvlsi designperformance evaluationmicroelectronicsoptoelectronicsparallel computinggpu computingelectrical engineeringhardware architecture

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Jose Renau

Department Chair Professor Professor

University of California, Santa Cruz

Affiliations

Baskin School of Engineering

Computer Science and Engineering

Jose Renau is currently serving as a Baskin School Of Engineering Department Chair Professor Professor at University of California, Santa Cruz.

Honors

Create free account to unlock more features

Experiences

Create free account to unlock more features

Education

Create free account to unlock more features

Jose Renau

University of California, Santa Cruz

Department Chair Professor Professor

You can click a keyword to filter the displayed items

Video Presentations

Notable Scholarly Works

Notable Federal Grants

Collaborators

Developing the Itl Framework and Committing to Inquiry as a Method for Reducing Equity Gaps in High-Impact, Computer Science and Engineering Courses. (2024)

Sagnik NathJennifer QuynnJose Renau

engineering educationequity gapscomputer scienceitl frameworkhigher educationengineering courses

A Multi-Threaded Fast Hardware Compiler for Hdls. International Conference on Compiler Construction (2023)

Sheng-Hong WangHunter James CoffmanKenneth MayerSakshi GargJose Renau

parallel computingcomputer engineeringcomputer sciencecompiler technology

Enabling Reduced Simpoint Size Through Livecache and Detail Warmup. BenchCouncil Transactions on Benchmarks Standards and Evaluations (2022)

Jose RenauFangping LiuHongzhang ShanSang Wook Stephen Do

performance benchmarkingbenchmarking toolsystems engineeringsimpoint sizebenchmark studiesmachine learningdetail warmup

Effective Processor Verification With Logic Fuzzer Enhanced Co-Simulation. IEEE/ACM International Symposium on Microarchitecture (2021)

Nursultan KabylkasTommy ThornShreesha SrinathPolychronis XekalakisJose Renau

co-simulationdefect tolerancehardware securitycomputer scienceeffective processor verificationlogic fuzzer

LIVEHD: A Productive Live Hardware Development Flow. IEEE Micro (2020)

Sheng-Hong WangRafael Trapani PossignoloHaven Blake SkinnerJose Renau

device developmentsystems engineeringengineeringembedded systemselectrical engineering

LIVESIM: A Fast Hot Reload Simulator for Hdls. (2020)

Haven SkinnerRafael Trapani PossignoloSheng-Hong WangJose Renau

Load Driven Branch Predictor (Ldbp). arXiv (Cornell University) (2020)

Akash SridharNursultan KabylkasJose Renau

decision tree learningbranch predictorapplied mathematicsmachine learning

Emi Architectural Model and Core Hopping. (2019)

Daphne I. GormanRafael Trapani PossignoloJose Renau

emi architectural modelarchitecturecore hoppingmodeling and simulationelectrical engineering

Smatch. (2019)

Rafael Trapani PossignoloJose Renau

GPU Ntc Process Variation Compensation With Voltage Stacking. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018)

Rafael Trapani PossignoloElnaz EbrahimiEhsan Khish ArdestaniAlamelu SankaranarayananJose Luis BrizJose Renau

systems engineeringengineeringvlsi technologyvlsi designperformance evaluationmicroelectronicsoptoelectronicsparallel computinggpu computingelectrical engineeringhardware architecture

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Similar Faculty Members

Dean Tullsen

Institution

University of California, San Diego

computer engineering

system software

David Andrews

Institution

University of Arkansas

hybridthreads

reconfigurable computing

Christopher Batten

Institution

Cornell University

design automation

hardware specialization

Roman L Lysecky

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design automation

embedded system security

Michael Huang

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computer engineering

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computer engineering

hardware architecture

Lizy K John

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big data

Janardhan Rao Jana Doppa

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industrial artificial intelligence

machine learning

Srinivas Katkoori

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design for testing

design automation

Anand Sivasubramaniam

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industrial informatics

parallel computing